Intel Foundry has released version 0.9 of its process design kit for the Intel 14A process node, giving external chip designers their first silicon-validated look at the upcoming manufacturing technology. The release provides early customers with physical test data to build test chips ahead of planned commercial production in 2028.
Key points
- Intel Foundry released version 0.9 of the 14A process design kit, shifting customer work from theoretical models to physical silicon measurements.
- The manufacturing process introduces second-generation RibbonFET transistors, PowerDirect backside power delivery, and specialised Turbo Cells for processor logic.
- Intel plans to release the final 1.0 kit in early 2027 before starting risk production later that year and commercial manufacturing in 2028.
- Design automation vendors including Cadence, Synopsys, Siemens, and Keysight have certified their tools for the new technology.
What the 14A PDK 0.9 release provides
A process design kit, or PDK, acts as the foundational manual and software library for semiconductor development. It supplies electronic design automation tools with transistor models, geometric design rules, and electrical characteristics. Without an accurate kit, engineers cannot design complex integrated circuits that behave predictably once fabricated in a cleanroom.
Early versions of such kits rely heavily on mathematical simulations and finite-element modeling. The release of version 0.9 marks a turning point because it incorporates actual measurements gathered from physical silicon test runs. Engineers can now model leakage current, switching speeds, and thermal constraints with real-world accuracy.
This level of data allows prospective customers to begin architectural work for risk production runs. By testing layout schemes against verified transistor characteristics, chip designers can resolve structural bugs and timing errors early, avoiding expensive redesigns when the production lines begin operating at scale.
Inside the 14A architecture
The 14A node serves as the successor to Intel 18A, refining the structural changes that Intel introduced on that earlier generation. The architecture relies on three primary technical additions designed to improve compute density and power efficiency.
First, the node incorporates RibbonFET 2, the company’s second-generation gate-all-around transistor implementation. Gate-all-around structures wrap the conductive control gate completely around horizontal silicon ribbons, eliminating current leakage that troubles older FinFET transistors at sub-two-nanometre dimensions.
Second, Intel is deploying PowerDirect backside power delivery. While the earlier PowerVia approach moved power distribution networks to the rear of the wafer using through-silicon vias, PowerDirect connects the power rails directly to the source and drain regions of the transistors. Removing the intermediate vias frees additional routing space on the front interconnect layers and lowers electrical resistance across the chip.
Third, Intel has added Turbo Cells to its standard-cell library. These standard cells help designers map timing-critical pathways in central processing units and graphics processors, extracting higher clock speeds without requiring broad, power-hungry overhauls across less critical parts of the die.
How does 14A build on 18A production?
Intel Foundry is applying operational lessons drawn from twelve months of running its 18A lines to accelerate the maturation of the 14A node. The factory network has faced intense scrutiny regarding yield curves and defect rates as the company attempts to compete directly with Taiwan Semiconductor Manufacturing Company.
To prevent similar delays, Intel expanded capital spending on inline defect inspection tools, predictive simulation models, and automated wafer metrology. Finding particulate contamination and lithographic anomalies earlier in the manufacturing cycle reduces the time required to complete engineering feedback loops.
The company also altered its relationships with outside tool and chemical makers. Instead of waiting for finished equipment to arrive at fabrication sites, Intel development groups now collaborate directly with suppliers during initial tool design, holding regular yield summits to address hardware limitations before high-volume machinery is locked down.
Ben Sell, corporate vice president of front-end technology development at Intel Foundry, said the milestone gives customers confidence as the node reaches maturity “supported by silicon-backed validation.”
The design tool ecosystem and commercial stakes
Attracting large semiconductor designers requires broad compatibility with standard design suites. Intel confirmed that several major design software companies have certified tool flows for the 14A technology.
Cadence has formed a design-technology co-optimisation partnership with Intel, tailoring artificial intelligence design engines and intellectual property blocks specifically to the node’s layout rules. Keysight, Siemens, and Synopsys have similarly validated their synthesis and verification software for version 0.9.
Despite this software support, Intel Foundry has not yet named any external commercial customers that have committed to tape-outs on the 14A node. Contract foundries require hundreds of millions of manufactured units to amortise the astronomical capital costs of modern extreme ultraviolet lithography plants.
Securing external fabrication contracts remains essential for Intel’s standalone manufacturing unit, which cannot rely solely on the company’s internal processor shipments to achieve profitability.
What happens next
Intel plans to release PDK version 1.0 in the first quarter of 2027. That release will certify the process as ready for high-volume manufacturing.
Ali Farhang, corporate vice president of Intel Foundry’s design technology platform organisation, said the team is focused on “sustaining this level of quality across future releases” as work moves toward the 2027 milestone.
Internal risk production of Intel’s own designs is scheduled to begin in the second half of 2027, followed by commercial mass production in 2028. Intel also plans subsequent performance variants, designated 14A-E and 14A-P, though specific delivery dates for those revisions remain unannounced.
