Chinese memory maker CXMT plans to ship its first engineering samples based on a 4F2 DRAM architecture from Hefei before the end of the year. The company confirmed that its sixth-generation memory platform uses the compact cell design and has passed initial engineering checks, directly challenging arguments raised by US competitor Micron over physical scaling limits.
Key points
- CXMT confirmed its sixth-generation memory platform relies on a 4F2 DRAM cell structure and passed internal engineering verification.
- The manufacturer plans to deliver functional engineering samples to partners before the close of the year.
- The project disputes Micron’s public technical argument that capacitor pitch, rather than cell layout, limits dynamic memory scaling.
The push for 4F2 architecture
Dynamic random-access memory relies on billions of microscopic cells, each consisting of a transistor and a capacitor storing a single bit of data. In standard manufacturing terminology, cell dimensions are measured against the minimum feature size, denoted as F. Mainstream commercial DRAM has long used a 6F² footprint, where each individual cell covers an area six times the square of that feature size.
A move to 4F2 reduces the surface area occupied by each memory cell by roughly one-third. That reduction allows fabricators to print more storage capacity onto a single slice of silicon. CXMT stated that its sixth-generation DRAM platform adopts this architecture to increase bit density across future silicon wafers.
Achieving a 4F2 layout requires manufacturers to change how transistors are placed on the die. Conventional planar transistors lie flat across the silicon substrate, which sets a hard limit on horizontal spacing. A 4F2 structure forces engineers to adopt vertical channel transistors, building the switch upward into the chip rather than sideways across its surface.
The dispute over capacitor pitch
CXMT’s timeline directly responds to industry scepticism led by Micron. The US chipmaker previously argued that redesigning memory cell layouts to 4F2 yields diminishing returns because capacitor pitch remains the principal obstacle to density improvements.
In DRAM production, capacitors must hold a sufficient electrical charge to prevent data corruption between refresh cycles. As cells shrink, maintaining that capacitance requires capacitors to become tall, narrow pillars with high aspect ratios. Micron contended that the physical distance between these charge-holding capacitors, rather than the transistor configuration underneath them, determines how tightly memory cells can be packed.
Micron argued that shrinking horizontal cell spacing without resolving capacitor stability risks electrical leakage and structural collapse during manufacturing. By preparing engineering samples for release, CXMT claims to have built a workable integration scheme that accommodates capacitor spacing constraints within a 4F2 layout.
Global competition in memory scaling
The transition toward vertical transistors and smaller cell profiles is a central contest among the world’s leading memory producers. South Korean manufacturers Samsung Electronics and SK Hynix have both run research programmes examining vertical channel transistors and 3D DRAM to bypass planar scaling barriers below 10 nanometres.
CXMT has operated under restrictions on acquiring Western semiconductor equipment, including advanced extreme ultraviolet lithography systems. Despite trade curbs, the company has expanded its domestic fabrication lines and broadened its product catalogue from older DDR4 memory into LPDDR5 and high-density chips for mobile devices and personal computers.
Pursuing 4F2 provides CXMT with a path to higher memory density without relying entirely on extreme feature-size reductions from advanced lithography tools. If vertical cell arrangements function reliably, CXMT can achieve competitive die capacities using mature lithography equipment combined with vertical etching and deposition processes.
Next steps for CXMT
CXMT stated that its sixth-generation silicon has passed verification testing for engineering samples, confirming that the underlying cell design functions under laboratory conditions. The company plans to provide these samples to selected partners before the end of the year.
Shipping engineering samples marks an early stage in commercial memory development. CXMT must still demonstrate acceptable manufacturing yields and data retention stability before committing the architecture to high-volume commercial production lines.
