DeepSeek is preparing to conduct the full pre-training run for its upcoming DeepSeek V5 model on Huawei Ascend 950DT processors instead of Nvidia hardware, according to reports circulating among semiconductor analysts. The project marks China’s first attempt to train a frontier foundation model from scratch using an entirely domestic computing stack.
Key points
- DeepSeek has ordered roughly 160,000 Huawei Ascend 950DT processors for a one-gigawatt data centre in Inner Mongolia.
- The upcoming DeepSeek V5 architecture will scale to roughly eight trillion parameters.
- The training run will use Huawei Atlas 950 SuperPoD clusters and DeepSeek’s custom TileLang compiler to bypass Nvidia’s CUDA ecosystem.
- Each Ascend 950DT processor costs roughly 111,000 yuan, placing the hardware order at around $2.56 billion.
The hardware backing DeepSeek V5
DeepSeek intends to train an eight-trillion-parameter system without relying on imported American accelerators, tech outlet Wccftech reported. The Chinese artificial intelligence laboratory has faced persistent procurement bottlenecks because export controls repeatedly restrict supplies of Nvidia chips, including the slowed H20 graphics card designed specifically for the Chinese market.
To bypass those limits, DeepSeek turned to Huawei Technologies. Deliveries of the 160,000 Ascend 950DT chips are scheduled to ramp up during the fourth quarter of 2026. The chips will populate a one-gigawatt facility in Inner Mongolia, where cooler ambient temperatures and access to local energy grids help offset the heavy electrical demands of high-density computing clusters.
The unit cost of an Ascend 950DT currently sits at around 111,000 Yuan or ~$16,000. That puts the hardware on par with street prices for Nvidia H20 units, which trade between $15,000 and $25,000 in regional distribution channels. The total capital expenditure for the purchase reaches an estimated $2.56 billion.
Semiconductor Manufacturing International Corporation manufactures the Ascend 950DT using its N+3 production technology, an advanced seven-nanometre-class process. Built on Huawei’s third-generation DaVinci v3 microarchitecture, the processor handles both training workloads and large-scale inference generation.
Each chip features 144 GB of specialized High Bandwidth Memory in the form of HiZQ 2.0 HBM. The package delivers 4.0 terabytes per second of memory bandwidth alongside a 2.0 terabyte-per-second card-to-card interconnect. The architecture provides native execution for low-precision formats, including FP8, FP4, and Huawei’s proprietary HiF8 numerical standard.
Cluster networking in the Atlas SuperPoD
Training an eight-trillion-parameter model requires high-speed communication across tens of thousands of individual dies. Huawei packages the processors inside its Atlas 950 SuperPoD architecture, connecting up to 8,192 Ascend 950DT units into a unified computing block that achieves eight exaflops of peak FP8 computing capacity.
In high-performance clusters, interconnect latency often causes training jobs to stall during gradient synchronisation. Huawei designed the SuperPoD inter-chip mesh to sustain two terabytes per second of bidirectional data exchange between adjacent nodes, preventing memory starvation during distributed tensor parallelism.
The engineering shift aligns with broader industry data tracking infrastructure development across the country. Earlier assessments found that China AI inference data overtakes model training as deployment expands, but premier laboratories still require dedicated high-density clusters to advance baseline reasoning capabilities.
Engineering teams have already run preliminary validation on smaller clusters. In trials on a 128-card Atlas installation, developers recorded read-phase performance of 410 teraflops on sparse attention operators. Those tests enabled specialised workloads to reach 95 percent of the chips’ theoretical FP8 mathematical peak during compute-bound operations.
Rewriting the software layer with TileLang
Raw silicon is only half the equation in frontier model development. Nvidia has maintained dominance over machine learning workflows for almost two decades because its CUDA platform serves as the default development environment. Chinese hardware designers have struggled to match Nvidia largely because competing software libraries often suffered from poor compiler efficiency and buggy drivers.
DeepSeek addressed that problem by developing an intermediate software stack tailored directly to Ascend silicon. The core of this effort is TileLang, an open-source kernel compiler designed to write hardware-neutral code. Rather than writing distinct kernels for different vendor architectures, engineers write algorithms in TileLang, while hardware manufacturers implement a single backend driver. Runtime engines then automatically select the fastest machine instructions.
Alongside TileLang, DeepSeek deployed several specialised mathematical libraries: DeepSelect for top-k filtering operations, DeepGEMM-Ascend for general matrix multiplication, DeepEP-Ascend for expert-parallel routing in mixture-of-experts models, TileKernels for vector memory access, and FlashMLA to accelerate multi-head latent attention.
This bespoke software adaptation improved hardware efficiency. Model FLOPS utilisation on the Ascend 950DT reached 45 percent under DeepSeek’s custom stack, according to engineering figures cited by Wccftech. Earlier deployments on Huawei’s older Ascend 910C hardware typically plateaued near 30 percent utilisation, where communication bottlenecks left processing cores idle.
What the training run means for Nvidia
A full pre-training run on domestic silicon represents a significant test for the global semiconductor market. If DeepSeek succeeds in pre-training an eight-trillion-parameter system without relying on CUDA, it proves that leading AI labs can build frontier software entirely outside the American hardware ecosystem.
Market analysts note that the shift is already visible in domestic purchasing trends. Industry estimates suggest Nvidia’s market share for artificial intelligence processors in China fell from roughly 95 percent to eight percent following successive rounds of trade sanctions, while Huawei expanded its share to around 50 percent.
Post-training experiments have already shown that Ascend clusters can handle fine-tuning and inference. What DeepSeek V5 tests is whether the combination of Ascend hardware and TileLang can sustain the stability required for months of uninterrupted pre-training at massive scale without catastrophic cluster crashes or hardware dropouts.
Shipments of the Ascend 950DT will continue arriving at the Inner Mongolia site through early 2027 as engineers prepare the full data centre for initial model runs.
